8 lu yu , feng yi , jie dong , cixun zhang . overview of avs - video : tools , performance and complexity . in proc 系統(tǒng)采用ddr sdram作為外存,每8個(gè)連續(xù)mb存儲(chǔ)到一個(gè)bank的一行里,能夠使bank沖突最少發(fā)生。
Ddr sdram memory bank is used as the mass buffer in some applications . compact pci 6u board is adopted because of its reliability 本處理板中還加入了一個(gè)ddrsdram內(nèi)存條,主要是考慮到實(shí)際應(yīng)用中可能需要大容量緩存。
The result of hardware debugging is a critical process because it decides success or failure of the design . simulation mainly realizes dsp , pci , ddr sdram interfaces and inter - communication which is the primary work for fpga design 仿真部分主要是對(duì)三種接口: dsp 、 ddrsdram 、 pci進(jìn)行fpga設(shè)計(jì),這中間涉及一些協(xié)議,是fpga設(shè)計(jì)的關(guān)鍵部分。
The b3g test tools implement high speed ( above gigabit bps ) data transmission using aurora protocol of xilinx . the b3g test tools save the high - speed data into ddr sdram and send the data to personal computer B3g測(cè)試工具基于aurora協(xié)議實(shí)現(xiàn)了高速數(shù)據(jù)流(傳輸速率為gbps )的傳輸,數(shù)據(jù)先保存在ddr內(nèi)存中,再通過(guò)串口將數(shù)據(jù)傳送到計(jì)算機(jī)上,以便對(duì)數(shù)據(jù)進(jìn)行分析。
High - effective and low - cost memory system the demand for bandwidth and response time of video decoder is analyzed , a high - effective and low - cost multi - entity interlaced ddr sdram controller design and relevant address mapping scheme is proposed 高效低成本的存儲(chǔ)系統(tǒng)設(shè)計(jì)本文分析了avs和h . 264解碼器對(duì)存儲(chǔ)系統(tǒng)帶寬和響應(yīng)速度的要求,針對(duì)ddrsdram延遲長(zhǎng)、多bank的特點(diǎn),設(shè)計(jì)了一套高效的多體交錯(cuò)式ddrsdram控制方案和相應(yīng)的地址映射方式。
Through using si analyse in the hardware design of a dtv set top box ( stb ) , the main contribution of this paper is to give a series of solutions for si problems according to theoretically analyse and real works . advanced measuring systems have also been shown in the paper . with the help of this paper , the stb system of a world famous corporation has successfully get wide using of ddr sdram 本文的主要工作是在針對(duì)消費(fèi)類電子( consumerelectronics )領(lǐng)域中的數(shù)字電視接收機(jī)頂盒進(jìn)行硬件設(shè)計(jì)的過(guò)程中,引入信號(hào)完整性分析的設(shè)計(jì)方法進(jìn)行高速數(shù)字電路的設(shè)計(jì),利用理論分析作為設(shè)計(jì)指導(dǎo),通過(guò)測(cè)量、仿真和實(shí)際布板的結(jié)果進(jìn)行驗(yàn)證,得出一系列針對(duì)信號(hào)完整性問(wèn)題的解決方案和設(shè)計(jì)流程,成功地解決了某世界著名企業(yè)的機(jī)頂盒系統(tǒng)中ddr存儲(chǔ)器工作頻率無(wú)法提高的問(wèn)題,在新一代的機(jī)頂盒產(chǎn)品中廣泛使用ddr存儲(chǔ)器,在很大程度上提高了系統(tǒng)的性能,滿足了市場(chǎng)的需求。
Followed above , this dissertation has much content about the hardware design which include dsp , fpga , ddr sdram memory bank interface circuit , pci , power circuit , board - level interconnection design . this part puts much emphasis on key circuits many of which require us to have deeply known the components adopted and involved specifications 這部分主要是對(duì)電原理圖的重要地方和需要注意的地方進(jìn)行重點(diǎn)闡述,包括dsp 、 fpga 、 ddrsdram內(nèi)存條接口電路、 pci接口電路、電源、板級(jí)互連等部分。